Some types of memory devices comprise memory cells that store data by programming the memory cells to respective programming levels, selected from among multiple predefined programming levels. Programming the memory cells can be carried out in various ways. For example, to program a group of memory cells using a program-and-verify scheme, the memory device applies a sequence of programming pulses to the memory cells in the group, and verifies the states of the cells between consecutive programming pulses.
Program-and-verify schemes are known in the art. For example, U.S. Patent Application Publication 2014/0198570, whose disclosure is incorporated herein by reference, describes a memory that stores multiple bits per cell and is operated by applying a one-pass, multiple-level programming, such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.
As another example, U.S. Patent Application Publication 2014/0219020, whose disclosure is incorporated herein by reference, describes a memory system that includes a nonvolatile memory device, and a memory controller that is configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed by one of a first program mode and a second program mode. At the first program mode, a plurality of logical pages corresponding in number to a maximum page number is stored at the memory cells, and at the second program mode, one or more logical pages the number of which is less than the maximum page number are stored at the memory cells using a bias condition that is different from that used in the first program mode.
A memory device is typically configured to store data in units of one or more pages. In some storage systems, however, the data available for storage at a given point in time may have a size that is different from the storage unit of the memory device.
Methods for handling the storage of data chunks whose size does not fit the storage unit of the memory device are known in the art. For example, U.S. Patent Application Publication 2015/0143029, whose disclosure is incorporated herein by reference, describes a memory system or flash card, which may include a controller that indexes a global address table (GAT) with a single data structure that addresses both large and small chunks of data. The GAT may include both large logical groups and smaller logical groups for optimizing write amplification. The addressing space may be organized with a large logical group size for sequential data. For fragmented data, the GAT may reference an additional GAT page or additional GAT chunk that has a smaller logical group size.
As another example, U.S. Patent Application Publication 2013/0227198, whose disclosure is incorporated herein by reference, describes a flash memory device and an electronic device employing thereof designed for efficiently processing data that is larger than a page size of a data block and for processing data that is smaller than the page size of the data block. The flash memory device preferably includes a plurality of flash arrays therein and the plurality of flash arrays is divided into partitions depending on at least two or more page sizes, thereby advantageously improving the performance of random write.